Google's senior director of supply chain infrastructure, Nikhil Cherian, revealed the company is developing both software and hardware solutions to address memory constraints in AI servers. The approach includes salvaging DDR4 modules from retired servers, designing custom adapters to connect older memory to next-generation servers, and importing retired servers for DDR4 removal. Cherian noted that AI has shifted from compute-constrained to memory-constrained, with high-performance memory consuming about 75% of an AI server's bill of materials. Goldman Sachs expects third-quarter PC DRAM prices to rise 18% to 23% and server DRAM 13% to 18%. Trendforce data shows spot prices for DDR4 8GB and DDR5 8GB reached $142 and $133 in August. Google's two new TPU ASICs this year feature memory-optimized designs, potentially reducing memory requirements by a factor of six, with the TPU8i chip packing 288GB of HBM3e memory.
Google is tackling the memory bottleneck plaguing AI servers with a dual-pronged approach: software and hardware development, and an internal recycling supply chain for DDR4 components. Nikhil Cherian, senior director of supply chain infrastructure at Google, disclosed the plans. The company is salvaging DDR4 modules from retired servers by designing custom hardware adapters that allow the older memory to be used with next-generation AI servers. Google also imports retired servers and removes their DDR4 modules for recycling.
Cherian noted that the AI industry has rapidly shifted from being compute-constrained to memory-constrained, with high-performance memory accounting for about 75% of the bill of materials for a given AI server. This demand is pushing memory prices higher. Goldman Sachs reported that DRAM prices will continue to climb in the third quarter, with PC DRAM expected to rise 18% to 23% and server DRAM 13% to 18%. Trendforce data shows that in August, spot prices for DDR4 8GB and DDR5 8GB reached $142 and $133, respectively.
On the hardware front, Google's two new TPU ASICs this year feature memory-optimized designs, which the company claims could reduce memory requirements by a factor of six. The TPU8i chip uses a dedicated hierarchical memory design and relies on a high-speed DDR5 memory architecture for host-level tasks, with each chip packing 288GB of HBM3e high-bandwidth memory.
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