TSMC’s 3nm, 2nm and CoWoS advanced packaging capacity remains in short supply as late Q3 2026 approaches, according to ChainCatcher.
NVIDIA and Apple continue to occupy a large share of advanced process and packaging resources. Amazon Web Services’ Annapurna unit has recently increased tape-outs for in-house AI chips and secured more 3nm capacity. MediaTek, beyond its smartphone chip business, is also competing for 2nm, 3nm and CoWoS-S/L capacity on the back of a major Google TPU order.
Market talk points to a fresh capacity reshuffle
The market has circulated reports that TSMC recently adjusted its capacity allocation. After MediaTek took on a major Google TPU order, the next-generation TPU v9 is set to use both TSMC’s CoWoS-L and Intel’s EMIB-T, prompting a slight adjustment in MediaTek’s 3nm and 2nm capacity planning.
At present, NVIDIA is TSMC’s main 3nm customer and surpassed Apple in 2025 to become the largest one. Demand for 2nm, by contrast, is mainly led by Apple and others. After Annapurna expanded its tape-outs, AWS moved up in priority for both 3nm and CoWoS allocation.
Expansion figures for 2nm and 3nm
TSMC began accelerating expansion in early 2026. By the end of October, monthly 2nm capacity at Fab 20 in Baoshan, Hsinchu, and Fab 22 in Kaohsiung will each reach 50,000 wafers, for a combined total of about 100,000 wafers. By the same point, monthly 3nm capacity in Southern Taiwan is around 185,000 wafers.
As of the end of September, overall capacity utilization stood at about 96.2%. For nodes from 16/12nm and below down to 2nm, utilization was at 100%.
CoWoS shortage spills over to outsourced packaging orders
Insufficient CoWoS supply is pushing advanced packaging orders outward. In the reported order-taking sequence, Siliconware Precision Industries, part of ASE Group, comes first, followed by Amkor and Powertech. Powertech’s related packaging and testing capacity is already fully loaded, with order visibility extending to 2028.