Odaily reported that Citrini’s jukan posted on X about a report from South Korea’s ETNews, saying TSMC is building out the supply chain for CoPoS. The supply chain work covers materials, components and equipment, and the stated target is to achieve mass production next year. The update focuses on the advanced packaging segment and the industrial preparation around CoPoS.
The report also described PLP as a technology that packages diced chips on a rectangular panel. Compared with WLP, a circular wafer-level packaging method, PLP can reduce wasted space around the edge area because it uses a rectangular panel format rather than a round wafer format.
Using a standard 600×600 mm rectangular panel as the reference, the chip output is about five to six times that of the mainstream 300 mm, 12-inch wafer. This output comparison was presented as the key numerical difference between PLP and conventional wafer-level packaging in the cited report.