advanced pack2026-08-24 06:06:30Semi Analysis flags V5 Technologies as an early CoPoS inspection play in advanced packagingSemi Analysis said V5 Technologies has emerged as one of the main beneficiaries in the CoWoS supply chain and has already moved into Taiwan Semiconductor Manufacturing Co.’s next-generation CoPoS process. The report argues that rising packaging density in AI chips is turning yield control into a central issue for TSMC and outsourced semiconductor assembly and test providers, sharply lifting demand for optical inspection tools. According to the report, V5 Technologies’ V530 Pro platform uses in-house AI image recognition algorithms and high-speed imaging hardware to detect surface defects in advanced packaging, including contamination, scratches and process residue. The company posted about NT$2.08 billion in consolidated revenue in 2025, up 188% year over year, while earnings per share reached NT$14.04, a record high. Monthly revenue in the first half of 2026 continued to hit new highs as customers expanded CoWoS, 3D packaging and panel-level packaging capacity. Semi Analysis also identified CoPoS as V5 Technologies’ next growth engine. The company has launched four CoPoS machine models, compared with two for CoWoS, and estimates total inspection demand for CoPoS at roughly twice that of CoWoS. Its demo systems are already undergoing customer testing, with three panel-level packaging customers in talks. V5 expects customer qualification as early as the fourth quarter of 2026 and volume shipments in 2027.970
TSMC2026-08-10 04:22:46TSMC pushes CoPoS and COUPE as AUO group companies line up around CPOTaiwan Semiconductor Manufacturing Co. is accelerating work on its CoPoS and COUPE silicon photonics technologies, while AUO-linked companies Epistar, Tyntek and LandMark Optoelectronics are assembling around the co-packaged optics, or CPO, theme, according to ABMedia. The report says the group is positioning itself across light emission, sensing and packaging as suppliers look for an early foothold in next-generation advanced packaging led by TSMC. ABMedia describes CoPoS as a packaging approach that replaces the traditional silicon interposer with a very large glass substrate, expanding the area available for integrating multiple high-performance GPUs and ASICs into a single package. But the report also notes that higher chip density intensifies heat and power problems in ultra-high-compute environments, where conventional electrical transmission and copper interconnects are approaching physical limits. Against that backdrop, CPO is being framed as a route to move part of the interconnect from electrical to optical signaling by integrating optical transceivers directly into the package. Economic Daily News, cited in the report, says AUO is handling packaging integration and testing, while Epistar, Tyntek and LandMark each focus on different optical components. Market observers cited by ABMedia expect the group’s validation work to convert into orders and revenue as TSMC’s CoPoS ecosystem moves toward volume ramp-up.2440
TSMC2026-07-24 08:15:17TSMC Faces CoWoS Capacity Limits as CoPoS Targets Higher AI Chip OutputTSMC’s CoWoS packaging is under heavy strain, with lead times stretching to 52–78 weeks and utilization near 98%. The company is now pushing CoPoS, a panel-based approach aimed at boosting AI chip packaging efficiency.440
TSMC2026-06-15 05:21:08TSMC Advances CoPoS Supply Chain With Mass Production Targeted for Next YearCitrini’s jukan said on X, citing South Korea’s ETNews, that TSMC is building a CoPoS supply chain covering materials, components and equipment, with mass production targeted for next year. The report also compared PLP with WLP, noting the output advantage of a 600×600 mm rectangular panel.860
