Meta AI has introduced MetaRoCE, a new RDMA transport protocol designed for AI workloads running over commodity Ethernet. According to Techub, the protocol departs from standard RoCE by treating the network as lossy rather than lossless, while shifting packet ordering, path selection, and recovery functions to the NIC layer. The stated goal is to address network bottlenecks that emerge during training across large-scale AI clusters. Meta said it plans to release the specification, a reference software implementation, and a compliance test suite through the Open Compute Project. Hardware support remains at an early stage. The protocol has already been validated on AMD Pensando programmable NICs, and implementations from other vendors are still in progress. The report said the announcement should be viewed more as an architectural decision than a purchasing one. MetaRoCE’s design choices include out-of-order delivery by default, native multipathing, fault tolerance in place of lossless networking, end-to-end congestion control, and topology independence. Techub cited MarkTechPost for the report, which said the protocol builds directly on Meta’s 2024 work on large-scale RoCE and its broader infrastructure evolution.

A MarsBit report argues that AI agents are changing storage from a passive persistence layer into part of the execution path itself. As agents continuously observe, reason, call tools, write back results and preserve state, the value of storage is no longer limited to saving data after a task is complete. The report says SSDs are beginning to take on functions tied to model weights, KV cache spillover, indexing, encryption, compression, lifecycle control and long-term memory, pointing to a broader shift toward programmable, functional SSDs. The piece lays out how this transition could play out on both devices and in the cloud. On the edge, SSDs may become the long-lived state layer for personal agents, holding local models, adapters, vector indexes, personal memory and tool traces. In cloud deployments, storage nodes could move closer to the inference path, handling shared prefixes, KV data, adapters, vector search and governance. The report cites Mooncake and NVIDIA CMX as examples of systems where storage is already participating in token production rather than merely holding cold data. It also argues that the rise of agent systems does not diminish HBM. Instead, HBM, HBF, DRAM/CXL and SSDs are likely to be re-tiered by speed, mutability, capacity, cost and governance needs. Existing AI SSD efforts from Phison, Longsys, Maxio and partners are presented as early industrial samples of this shift, where the focus is moving from faster disks for AI workloads to a reallocation of responsibilities across runtime, memory hierarchy, controllers and flash.

Shenzhen-based Yunbao Smart has had its application for a ChiNext IPO accepted by the Shenzhen Stock Exchange, putting the chip startup on track to pursue the label of China’s first listed DPU company. Founded in August 2020 by Stanford PhD Xiao Qiyang, the company focuses on data processing units, a segment that gained attention after Nvidia introduced the DPU concept and Jensen Huang outlined the “CPU+DPU+GPU” architecture. According to the prospectus cited in the report, Yunbao Smart developed what it describes as China’s first high-performance, general-purpose programmable DPU SoC chip, with network bandwidth of 400 Gbps, four times the performance of traditional solutions, and power consumption cut by more than 50%. The company said it moved from FPGA verification to 6nm SoC mass production in four years. Financially, revenue rose from RMB 170,000 in 2023 to RMB 36.35 million in 2024 and RMB 370 million in 2025, while net losses were RMB 667 million, RMB 600 million, and RMB 1.19 billion over the same period. Tencent, which first invested in the angel round and kept backing later financings, held 19.7792% before the IPO through affiliated entities, making it Yunbao Smart’s largest shareholder. The report said the company’s valuation exceeded RMB 14 billion after a funding round in late November 2025.

Solayer is positioning itself as a hardware-accelerated blockchain project built around InfiniSVM, targeting over 1 million TPS and 100+ Gbps bandwidth. While the technology narrative is ambitious, LAYER remains far below its peak, making execution and adoption the key issues for the market.

Solayer is positioning itself as a hardware-accelerated scaling project for the Solana ecosystem, combining restaking, programmable networking, and multi-executor architecture to pursue ultra-high throughput and low latency.