Infineon Technologies said on Sept. 16 that it will sell its NOR Flash and F-RAM business to Winbond Electronics in a $1.12 billion deal, with closing targeted for the second half of 2027. Winbond plans to run the business as a standalone company based in San Jose, California, and bring back the Spansion brand, a name that disappeared after Spansion was folded into Cypress in 2015. The transaction does not cover Infineon’s entire memory portfolio. SRAM, HYPERRAM, nvSRAM, and radiation-hardened memory based on SONOS technology will remain with Infineon and continue serving automotive, industrial, infrastructure, aerospace, and defense markets. The report says Winbond sees strategic value in buying an established memory business with more than 30 years of experience, an existing supply chain, R&D operations, and customer relationships in sectors where qualification cycles are long. Infineon, for its part, said it will sharpen its product portfolio and capital allocation around core growth areas, as it continues to expand in automotive, power semiconductors, and AI data center power management.

Elite Semiconductor Memory Technology Inc. (ESMT, 3006) reported July revenue of NT$6.785 billion, up 40.02% from June and 491.06% from a year earlier. Revenue for the first seven months of the year reached NT$27.998 billion, compared with NT$7.339 billion in the same period last year, a gain of 281.48%. In its monthly filing, the company said the increase was driven by product market supply-and-demand factors, without adding further detail. ESMT’s product lines include DRAM, SRAM and flash memory. Separately, on Sept. 7, the company disclosed on behalf of subsidiary Cheng Feng Investment that it had acquired ESMT common shares. The transaction covered 1,082,941 shares at an average price of NT$301 per share, for a total of NT$326 million. The filing said the purchase was approved by the chairman on Sept. 7, and the cumulative shareholding ratio reached 0.36%. The average purchase price sat close to the stock’s 52-week high range, with ESMT having closed at NT$297 on Sept. 7 and traded between NT$291.5 and NT$306 on Sept. 8 before ending at NT$298.5.

Morgan Stanley has sharply raised its estimates for Google’s TPU-related revenue, projecting that the business could generate $108 billion annually by 2028 based on deployment pricing, backlog and shipment assumptions. The report adds weight to a broader view that Google’s Tensor Processing Unit program is shifting from an internal AI infrastructure tool into a standalone chip business. At SEMICON Taiwan, Google AI infrastructure SVP and CTO Amin Vahdat said TPU releases have moved from a two-year cycle to one generation a year, with a target of two releases annually. Google also said Taiwan is now its largest hardware engineering base outside the U.S., with R&D expansion centered in Taipei’s Shilin district. The article also points to a wider supplier base that now includes Broadcom, MediaTek and Marvell, alongside a commercial shift from cloud-only TPU access to direct sales of physical TPU systems for customer-owned data centers. Morgan Stanley raised its Google Cloud TPU-related revenue estimates to $7 billion for 2026, $84 billion for 2027 and $108 billion for 2028, while GF Securities expects TPU shipments to rise from 2.76 million units in 2024 to 8.8 million in 2027.

More than a dozen semiconductor companies—including Megawin, Geehy, LKS, Nuvoton, NXP, MindMotion, and GigaDevice—released new MCU products targeting home appliance applications in recent months. The wave of launches spans motor control SoCs, touch-enabled 8051 MCUs, ultra-low-power USB MCUs, and Matter-ready Wi-Fi modules. Industry Online projects China's home appliance MCU market will reach 13 billion yuan in 2025, with 32-bit MCUs becoming the mainstream choice over legacy 8-bit and 16-bit parts. Price competition has intensified dramatically: some Cortex-M0 MCUs now sell for as little as 0.41 yuan (roughly $0.06) on e-commerce platforms. Vendors are trimming peripherals and resource configurations to hit rock-bottom price points, while engineers debate whether Matter connectivity upgrades could open the next growth chapter for the segment.

At SEMICON Taiwan 2026, Google Cloud senior director Nikhil Cherian said AI workloads are now memory-bound, with high-performance memory exceeding 75% of AI server hardware BOM cost. Google unveiled a two-pronged approach: TPU 8i (288GB HBM, 384MiB on-chip SRAM, zero off-chip latency) and TPU 8t (9,600 chips, 2PB pooled HBM) to split inference and training, plus a training-free lossless quantization algorithm called TurboQuant that compresses KV cache from 32-bit to 3-bit, cutting memory footprint sixfold and accelerating attention computation 8x. The algorithm also integrates older DRAM technology to extend component lifecycle.

OpenAI says its in-house Jalapeño inference chip, developed with Broadcom, outperformed Nvidia’s GB300 on power efficiency and response time in internal testing, according to remarks by chip lead Richard Ho at Stanford University’s Hot Chips conference. The chip is designed for inference rather than model training and was formally introduced in June after a development cycle that OpenAI says took nine months from project start to tape-out. A 128-chip Jalapeño system delivers 1.7 exaFLOPS of 4-bit MXFP4 compute, or about 13.4 petaFLOPS per chip, and includes 27.5 TB of HBM4 memory. Technical analysis cited by The Register said the system posted 1.5x to 1.9x higher peak throughput and 1.7x to 3.6x lower end-to-end latency in OpenAI’s custom InferenceX benchmark, with even larger gains in ultra-low-latency scenarios. Bloomberg, however, said the results come with at least four caveats: Jalapeño was not compared with Nvidia’s newer Vera Rubin chips; speculative decoding was excluded from the benchmark; the system trails Nvidia GB200 NVL72 and GB300 NVL72 racks in raw compute and memory capacity; and OpenAI has not disclosed actual power draw. The report added that volumes will remain limited in 2026, with mass production only expected in 2027.

Ingenic rang the opening bell in Hong Kong on Aug. 25, debuting at HK$100 per H share and reaching an opening market capitalization of about HK$51.5 billion. The company had already been listed on Shenzhen’s ChiNext board since May 31, 2011, and the new listing places it among semiconductor companies with both A-share and H-share listings. The prospectus outlines a chip platform strategy built across three product lines: memory, compute and analog. That structure took shape after Ingenic completed its acquisition of Beijing Silicon and indirectly took control of Integrated Silicon Solution Inc. (ISSI) in 2020. Since then, the company has operated around three brands: ISSI for memory, Ingenic for compute and Lumissil for analog. Its recent numbers show a rebound. Revenue moved from RMB 45.31 billion in 2023 to RMB 42.13 billion in 2024, then back up to RMB 47.41 billion in 2025. First-quarter 2026 revenue reached RMB 15.60 billion, up 47.1% from a year earlier, while net profit rose to RMB 3.20 billion and gross margin climbed to 42.6%. Ingenic said it expects to raise HK$3.13 billion from the Hong Kong offering. Half of the proceeds are earmarked for R&D, while 25% is set aside for strategic investments and acquisitions.

High Bandwidth Memory is no longer being framed as a standalone memory problem. At Hot Chips 2026, Samsung and SK Hynix both argued that GPUs, memory, foundry processes and packaging now have to be designed as one system, but the two companies outlined sharply different routes. Samsung is trying to turn the HBM base die from a passive bridge into an active logic layer, moving the memory controller off the GPU, adding memory expansion and selective compute to the base die, and ultimately aiming for zHBM, a structure that vertically stacks DRAM directly on top of compute silicon. Samsung said that approach could free up 5% to 10% of GPU area, lift performance by 10% to 20%, cut DRAM power by about 70%, and deliver more than 2.3x the bandwidth of HBM4E. SK Hynix, by contrast, is concentrating on higher stack counts and the thermal and warpage penalties that come with them. The company said 12-high HBM4 is in production and 16-high parts are in customer validation, while hybrid bonding remains in R&D for 20-high and above. It also presented iHBM, a thermal path built into the hottest region of the stack. Micron took a third angle, arguing that the AI memory wall is widening as accelerator compute rises faster than attached-memory bandwidth, forcing increasingly difficult trade-offs across bandwidth, capacity, packaging complexity, heat and reliability.