PANews contributor animajoe0917 wrote that two developments on Aug. 4, 2026 reshaped how the memory sector should be read. In the morning, SK hynix and SanDisk introduced the first standard specification for high-bandwidth flash, or HBF, at FMS 2026, setting out a new memory tier between HBM and SSDs. Later the same day, TrendForce reported that Nvidia was evaluating a lower HBM setup for Rubin Ultra, moving away from the original 12hi HBM4E plan and reviewing HBM4E 8hi, HBM4 12hi, and HBM4 8hi in parallel.
The article noted that Micron rose 3.68% in premarket trading that day, SK hynix gained 3%, and SanDisk climbed 4.42%. Its conclusion was not that a broad memory boom had arrived. The point, instead, was that value allocation across the storage stack is being rewritten, with interconnects, not just NAND process progress or packaging improvements alone, taking the central role.
The bottleneck is shifting location
The article framed the core thesis as a migration of bottlenecks. At GTC in March 2026, Nvidia introduced the Vera Rubin platform. Two numbers defined the change: NVLink 6 delivered 3.6 TB/s of bidirectional bandwidth per GPU, twice the level of Blackwell, and the NVL72 rack reached 260 TB/s of total interconnect bandwidth, linking 72 Rubin GPUs and 36 Vera CPUs in a fully connected design.
What mattered more than the raw increase, the article argued, was which layer was growing faster. In the Blackwell era, single-card HBM3E bandwidth at 8 TB/s stood far above NVLink 5 at 1.8 TB/s, leaving chip-to-chip communication as the tighter point. By the time of Vera Rubin, HBM4 bandwidth had doubled to about 1.2 TB/s per card, while NVLink 6 had grown by more than 2x. At the same time, cluster scale had expanded from thousands of cards to hundreds of thousands, and inter-chip traffic was growing faster than per-card memory bandwidth. The article described that as a structural move from asking whether one card could be fed fast enough to asking whether 100,000 cards could talk to each other efficiently. It assigned five stars to that claim and cited official GTC 2026 data.
Seven developments from March to August point to the same process
The article linked a sequence of milestones from March through August 2026:
- March 2026 GTC: NVLink 6 at 3.6 TB/s and 260 TB/s of rack-level bandwidth.
- July 2026: Nvidia Spectrum-X CPO shipments, which the article said brought CPO mass production forward by two years.
- July 2026: Eoptolink H1 growth of 78%-103%, with 1.6T accelerating in Q3 and Q4.
- July 2026: Intel introduced EMIB-T, and MediaTek confirmed a dual-route approach using both EMIB-T and CoWoS.
- August 2026: TSMC was described as drawing on EMIB-like ideas in work with Kinsus.
- August 2026: HBF standards were released, UCIe could connect directly to CPUs and GPUs, and Google joined the effort.
- August 2026: Nvidia evaluated lower HBM configurations.
Viewed separately, each item was a news event. Taken together, the article said, they formed one chain: interconnect bandwidth was expanding at speed, packaging was beginning to break a monopoly structure, HBM was being actively scaled down in some plans, and a new memory tier was being born through interconnect buses. The process was described as a move in which the bottleneck shifts from inside the compute unit to the interconnect layer. In that reading, interconnects are no longer just links between GPUs in a data center. They are becoming the mechanism that reshapes the full compute-and-storage pyramid.
A five-layer pyramid of repricing
Layer 1: optical and electrical interconnects
The article ranked optical and electrical interconnects as the most important current bottleneck and gave the segment five stars. Its reasoning was that copper interconnects had already been pushed close to their physical limits inside NVL72 racks, and the next generations, NVL144 and NVL288, would need optics inside the rack. In that setting, interconnect bandwidth growth continued to outpace memory bandwidth growth.
The metrics listed in the piece included 3.6 TB/s of bidirectional bandwidth per GPU for NVLink 6, 260 TB/s of total interconnect bandwidth for NVL72, 400 Tb/s for Nvidia Spectrum-X CPO with shipments already underway, and continued low-volume shipments of Broadcom’s 51.2T Bailly CPO. TrendForce was cited as projecting the CPO/NPO market at more than $390 billion by 2030. The article also listed corporate figures: Eoptolink posted net profit of RMB 7 billion to RMB 8 billion in H1 2026, up 78%-103% year over year; Innolight reported Q1 2026 revenue of RMB 19.5 billion, up 192%; and TFC Communication guided H1 2026 net profit to RMB 1.12 billion to RMB 1.30 billion, up 25%-45%. It said the shipment ramp for 1.6T optical modules would accelerate in Q3-Q4 2026, that Eoptolink expected silicon photonics products to make up a sharply higher share of shipments, that Innolight’s Hong Kong IPO stood at HK$55 billion, about $70 billion, with 3.2T and silicon photonics in preparation, and that hyperscale cloud AI capex in 2026 would exceed $700 billion, citing CoBank.
The article’s view was that interconnect is the only track that combines the fastest growth, a hard structural shift from copper to optics, and a broad enough industrial chain for stock selection. It also listed risks: valuation pressure, including Innolight at 81x TTM P/E, the physical limits of silicon photonics, and a possible turn in capex growth.
Layer 2: advanced packaging
Advanced packaging was described as the physical foundation of interconnects and was rated four-and-a-half stars. The article argued that the ultimate constraint on interconnect bandwidth does not sit in the cable or fiber itself, but in the physical wiring between chips. When packaging supply expands will directly shape the rollout of CPO and chiplet-based hybrid packaging.
It said TSMC’s CoWoS capacity remained under heavy strain. Citing a July 30 report from The Information, the article said TSMC was working with Kinsus on an “EMIB-like” packaging approach because CoWoS silicon interposers were too costly and capacity-constrained in large chiplet scenarios. That TSMC was borrowing from Intel’s EMIB route was presented as evidence that CoWoS bottlenecks had become severe.
Intel, meanwhile, showcased EMIB-T at IEEE ECTC 2026, introducing TSV-based vertical power delivery inside the silicon bridge. The article cited supply-chain information saying EMIB-T carries costs 50% lower than CoWoS, with 98% yield and large-scale production in 2027. MediaTek said in its Q2 results that its AI ASIC projects use both EMIB-T and CoWoS. The piece also said Intel 18A had already secured customers including AMD, Nvidia, Marvell, Microsoft, Micron, and OpenAI, with yield at 85%.
In the comparison table cited by the article, Intel’s side featured 18A yield of 85% and a first-mover position in High NA EUV, while TSMC was listed at monthly 3nm capacity of 180,000 wafers in Q4E, with 2nm on the way. Packaging-wise, Intel offered EMIB-T with 50% lower cost and 98% yield, while TSMC still led with CoWoS but faced capacity pressure while developing an EMIB-like alternative. The investment implication in the article was that packaging could move from a near-single-supplier setup to a dual-supplier structure, reducing one constraint on interconnect growth and creating a second-order catalyst for that theme.
Layer 3: HBM
The article called HBM a bottleneck that has already been priced in and gave it four stars. HBM remains the memory closest to AI GPUs, with the highest bandwidth and the shortest physical distance to compute. But the article argued that supply constraints are moving from a short-term issue to a structural one, where the marginal cost of adding HBM capacity is beginning to outweigh the marginal return.
The market is controlled by three players, the article said, with Samsung at roughly 39% share, followed by SK hynix and Micron. The roadmap remains HBM3E to HBM4 to HBM4E. Bank of America was cited as forecasting growth from about $350 billion in 2026 to $2.46 trillion in 2030, roughly a sevenfold increase.
The article’s turning point came from TrendForce’s Aug. 4 report. Starting in Q3 2026, Nvidia was said to be evaluating Rubin Ultra memory configurations in parallel, replacing the original 12hi HBM4E setup with HBM4E 8hi, HBM4 12hi, and HBM4 8hi options. The article added that several cloud service providers were also considering lower HBM capacity for in-house ASICs. The reasons it gave were continued DRAM shortages into 2027 and uncertainty around validation progress for HBM4E 12hi.
Its argument was that when the best-funded buyers begin cutting memory configurations on purpose, HBM’s supply constraint has become structural rather than merely cyclical. The article still said HBM is irreplaceable, especially in latency-sensitive inference with batch size 1, where HBM bandwidth remains the top constraint. But as an investment case, it characterized HBM as linear improvement through stack count and TSV density, not architectural reconstruction. With a three-player oligopoly already well recognized, and with Nvidia trimming plans while HBF standards appear next door, the article concluded that HBM still has allocation value but less room for excess upside.
Layer 4: HBF
HBF was presented as a genuinely new category and received three-and-a-half stars. The article stressed that HBF is not trying to replace HBM. It is intended to fill a gap created by HBM’s high cost and limited capacity. In the inference era, it said, the “memory wall” is more a capacity wall than a bandwidth wall.
According to the first standard released on Aug. 4, HBF uses 8-layer or 16-layer NAND stacks and can reach 512 GB in capacity. It offers three bandwidth grades ranging from 0.4 TB/s to 3.0 TB/s, uses the UCIe interface, and sits between HBM and SSDs as a new memory tier. The alliance behind it includes SK hynix and SanDisk, with the specification published through OCP after six months of work. Google and Tenstorrent had already joined, and a Google DeepMind roundtable was scheduled for Aug. 6.
The logic, as laid out in the piece, is to use stacked NAND for high bandwidth and connect it tightly to CPUs and GPUs through UCIe. Compared with HBM stack capacities of 24 GB to 36 GB, HBF at 512 GB is an order-of-magnitude jump. It also said HBF Grade 3 at 3.0 TB/s exceeds HBM4 on bandwidth. The article repeated that HBF is not there to replace HBM. It is aimed at a gap created by HBM’s price and capacity limits, especially in inference, where KV cache can run into tens or hundreds of gigabytes and where the need is a larger near-compute storage pool, not necessarily the 8 TB/s extreme bandwidth of HBM.
Google DeepMind’s participation was described as practical rather than symbolic, because its own inference infrastructure has already hit that capacity wall. The article also made a broader point: HBF exists not because NAND alone made a breakthrough, but because interconnect bandwidth through UCIe reached a point that made the category possible. Without UCIe, it said, there is no HBF. That made HBF a proof point for the claim that interconnects can redefine storage value. The article gave the segment three-and-a-half stars, noting that while the OCP standard and alliance are real, mass production is still at least two years away.
For beneficiaries, it named SanDisk, SK hynix, and Micron. It said SanDisk, as one of the two main HBF alliance members, had risen 4600% after its split and carried gross margin of 78.4%, a sign that the market was not simply pricing NAND but pricing a new role for NAND as an AI platform component. For China-related mapping, the article mentioned YMTC on NAND and VeriSilicon and Montage on UCIe and chiplets, while noting that HBF’s packaging and stacking requirements are high and difficult to enter in the short term.
Layer 5: CXL memory pooling, plus DDR5 and NAND
The article described CXL memory pooling as a longer-dated option on the interconnect thesis and gave it three stars. CXL is not just “more memory,” in this view. It is a way to separate memory from the server box and pool it through an interconnect bus, which makes it a natural extension of the same logic.
The developments listed were Montage Technology’s pilot production of a CXL 3.2 MXC chip at 64GT/s, with entry into Samsung and SK hynix supply chains, described as the first time a Chinese controller chip reached Korean original manufacturers; Meta using CXL to recycle old DDR4 and cut server count by 25%; and Marvell launching the Tanzanite end-to-end CXL platform. Even so, the article said the ecosystem is not mature enough. CXL-aware operating systems, memory orchestration, and application adaptation remain early, and true large-scale deployment will likely wait until 2027 to 2028. For now, the article said, it belongs on a watchlist rather than as an immediate purchase.
DDR5 and NAND were placed further down the hierarchy, with three stars and two-and-a-half stars respectively. DDR5 was described as a natural volume beneficiary of rising CPU core counts in AI servers, without an independent extra catalyst. NAND was treated as a separate cyclical track: training workloads do not depend on storage bandwidth, and inference growth on the NAND side is more about capacity than about performance bottlenecks. Both still have allocation value, the article said, but neither sits on the priority line of the bottleneck-migration framework.
Investment mapping and Marvell’s special role
In the article’s investment table, optical and electrical interconnects held the top priority, with representatives including Innolight, Eoptolink, TFC Communication, and the U.S.-listed names $COHR, $LITE, $AAOI, $MRVL, $AVGO, and $SIVE. The stated logic was direct exposure to the bottleneck and participation in architectural change, with the main volume ramp expected in H2 2026 through 2027.
Advanced packaging came next, represented by Intel, TSMC, and packaging-equipment suppliers, tied to the opening of interconnect supply capacity and the weakening of CoWoS dominance. HBM followed as the installed base case, represented by SK hynix, Samsung, and Micron, with persistent supply tightness but narrowing upside elasticity. HBF was placed as a 0-to-1 category led by SanDisk, SK hynix, and $MU, where 2026 to 2027 would be about narrative and 2028 onward about earnings. CXL memory pooling, represented by Montage Technology and $MRVL, was framed as a 2027-2028 watch item. DDR5 and NAND stayed in the lower tiers under server shipment growth and independent cycle logic.
The article singled out Marvell. It said Marvell spans DSP, Teralynx switch chips, custom ASICs, and CXL, making it a full-stack supplier for interconnect infrastructure. Teralynx 10, built on 3nm and rated at 100.4 Tb/s, together with custom ASIC exposure, was described as not yet fully priced by the market. If interconnect is the leading theme, the article argued, Marvell’s portfolio value is not below that of optical modules themselves.
Risks listed in the article
The article ended with five risks. First, HBF is still a specification, not a shipping product, and large-scale deliveries may not happen until 2028 at the earliest. That means 2026 and 2027 are mostly a story-driven period rather than one validated by earnings, and the valuation behind SanDisk’s 4600% gain and 78.4% gross margin still needs to be tested.
Second, the AI capex cycle could turn. If growth slows from the $700 billion-plus level in 2027, both interconnect and HBM growth would come under pressure. Third, there are technology-route risks: silicon photonics modulators are approaching physical limits, while next-generation options such as thin-film lithium niobate and polymer-based modulation are not yet mature. Fourth, valuation remains a clear issue. The article cited P/E multiples of 81x for Innolight and 65x for Eoptolink, saying current prices imply continuing upside surprises in volume. If the 1.6T ramp or silicon photonics progress disappoints, elasticity could contract quickly. Fifth, geopolitics remains a factor. If export controls on optical modules or optical engines tighten, the A-share names Innolight, Eoptolink, and TFC Communication would likely be affected first, while U.S.-listed names such as $COHR, $LITE, $AAOI, $MRVL, and $AVGO appear more diversified.