Samsung Electronics introduced its V10 Bonding V-NAND, or BV-NAND, prototype at the Future of Memory and Storage conference in Santa Clara, California, held on Aug. 4 U.S. time, according to a report cited by PANews from Jin10. The company said the chip has more than 400 layers and uses a new wafer-bonding architecture designed to raise storage density and improve performance. Samsung said BV-NAND delivers about 58% higher storage density than its previous-generation V9 NAND, while also improving read, write, and input/output performance to meet rising demand from AI systems for higher-capacity and more energy-efficient storage.
Samsung also presented what it described as the industry’s first zHBM and zNAND-O architecture concept models. The design vertically stacks memory units so more data can be stored in a smaller space. Unlike conventional HBM packaging, which places memory alongside an AI processor, Samsung’s zHBM stacks memory directly above an AI accelerator. The company said this shortens data transfer distance, increases bandwidth, improves energy efficiency, enables storage density of more than 10 times that of conventional HBM5 memory, and cuts thermal resistance by more than half.
Samsung Electronics introduced its V10 Bonding V-NAND, or BV-NAND, prototype at the Future of Memory and Storage (FMS) conference in Santa Clara, California, on Aug. 4 U.S. time, according to a Jin10 report cited by PANews.
The chip has more than 400 layers and uses a new wafer-bonding architecture aimed at increasing storage density and improving performance.
Samsung said BV-NAND raises storage density by about 58% compared with its previous-generation V9 NAND. The company also said the technology improves read, write, and input/output performance as AI systems demand storage with higher capacity and better energy efficiency.
Samsung also showed zHBM and zNAND-O concepts
At the event, Samsung presented what it described as the industry’s first zHBM and zNAND-O architecture concept models. The approach vertically stacks memory cells so more data can be stored in a smaller footprint.
Instead of packaging high-bandwidth memory beside an AI processor, as in conventional HBM designs, Samsung’s zHBM places memory vertically on top of an AI accelerator. Samsung said that layout shortens data-transfer distance, boosts bandwidth, and improves energy efficiency.
The company added that its wafer-bonding technology could deliver storage density of more than 10 times that of conventional HBM5 memory, improve energy efficiency by 3x, and reduce thermal resistance by more than half.
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