Samsung Electro-Mechanics is working with Qualcomm on organic bridge technology designed for 2.1D packaging, with development and validation said to have been underway for more than a year. The bridge is described as similar in function to the silicon bridge used in Intel’s EMIB, but built with organic materials through substrate processes to connect multiple semiconductor chips inside a single package. Samsung Electro-Mechanics has embedded the organic bridge into grooved FC-BGA substrates to link Qualcomm chips and test performance and reliability. Qualcomm is considering the technology for large multi-chip semiconductors used in data centers and filed a related patent application in October 2024. Samsung Electro-Mechanics is also pursuing the same technology with several other customers. The target specifications call for 5 to 7 redistribution layers, line width and spacing of 1.5 to 2 micrometers, vias of 4 to 5 micrometers, and an inter-chip pattern density of 500 to 1,000 per millimeter. The company is producing evaluation samples internally, reviewing outside supply options, and conducting packaging assessments with Samsung Electronics’ foundry business.
Samsung Electro-Mechanics and Qualcomm are jointly developing organic bridge technology for 2.1D packaging, according to ChainCatcher. Development and validation have been underway for more than a year.
The organic bridge is described as similar to the silicon bridge used in Intel’s EMIB, but it uses organic materials and is made through substrate processes. Its role is to connect multiple semiconductor chips within the same package. Samsung Electro-Mechanics has embedded the organic bridge into a grooved FC-BGA substrate, connected Qualcomm chips to it, and evaluated performance and reliability.
Qualcomm is considering the technology for large multi-chip semiconductors for data centers and filed a related patent application in October 2024. Samsung Electro-Mechanics is also developing the technology in parallel with several other customers.
The target specifications call for 5 to 7 redistribution layers, line width and spacing of 1.5 to 2 micrometers, vias of 4 to 5 micrometers, and an inter-chip pattern density of 500 to 1,000 per millimeter. Samsung Electro-Mechanics is internally producing evaluation samples, reviewing external supply options, and working with Samsung Electronics’ foundry business on packaging evaluation.
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