Taiwan Semiconductor Manufacturing Co. said its 5.5x reticle-size CoWoS packaging has formally entered mass production, with product yields holding above 98%, according to public remarks made on Aug. 11 by Ho Chyun, the company’s vice president of advanced packaging. He also said TSMC is targeting 14x reticle-size CoWoS by 2029 and warned that ABF substrates are set to become the next tight point in the AI packaging supply chain after memory.
CoWoS output has expanded sharply over the past three years
Ho said TSMC’s CoWoS capacity has almost doubled year after year during the past three years. The company now operates 10 advanced packaging fabs worldwide, and total supply is much closer to customer demand than before, though it still has not fully met that demand.
He said he has worked in packaging since the 1990s and had never expected advanced packaging to post this kind of exponential growth in recent years. CoWoS, he added, has even become a widely recognized term in Taiwan. Ho joked that introducing himself has become very simple: 「Hi, I m the CoWoS guy」.
On yields, Ho said mass production results for 5.5x reticle-size CoWoS have been strong. Products for several AI customers have stayed above 98% for a long period, and some have exceeded 99%, which he said reflects TSMC’s process control in very large-area packaging.
SoIC is moving to a finer pitch, while chiplets are being used to cut cost
As CoWoS keeps moving to larger reticle sizes, TSMC is also advancing its SoIC hybrid bonding technology. Ho said 6-micron bonding pitch entered mass production last year, and the company expects to reduce that to 4.5 microns by 2029. At that point, he said, A14 chips could be stacked directly on A14 chips in a 3D structure, with interconnect density more than 50 times higher than conventional approaches and energy efficiency improved by 5 times.
Ho said the value of a chiplet strategy is not limited to getting around reticle-size constraints. It also allows analog circuitry and compute modules to be designed separately, so customers do not need to migrate every function to the newest process node, which lowers overall development cost.
TSMC has also introduced die matching algorithms to select the most compatible die combinations and improve performance consistency at the packaging level, Ho said. He compared the role to 「the world’s largest dating app」: customers provide complex matching algorithms, and TSMC uses its global manufacturing network to find each die its best 「soulmate」 before assembling and delivering the final product on schedule.
System-level interactions are becoming harder to ignore
Ho said the old method of validating only the chip and the package itself is becoming less effective as AI package sizes expand quickly. Once CoWoS goes beyond 3x reticle size, interactions among the package, the circuit board, the thermal structure and the full system become much more complex. To keep total failure rates for large AI systems within an acceptable range, the quality standard for a single packaged component must exceed automotive-grade requirements, he said.
To address that, TSMC is promoting an STCO, or System-Technology Co-Optimization, framework. Under that approach, chip, package, substrate, PCB and thermal design are optimized together before mass production, with real system thermal, mechanical and reliability boundary conditions brought into the early development process.
Ho cited a case in which the same chip, once integrated into different systems, showed die-edge damage that had never appeared during component validation. The issue eventually required joint adjustments with customers to PCB layout, passive component placement and manufacturing flow. In his account, that shows system boundary conditions have become a critical variable in validating large AI packages.
ABF substrates could be the next bottleneck after memory
Ho said the AI supply chain will face pressure from shortages in both memory and ABF substrates over the next few years. Customers have broadly adopted multisourcing to secure substrate capacity, but differences in thermal expansion coefficients and mechanical properties across suppliers are making coplanarity control and yield management harder during system integration and delivery. In that sense, he said, multisourcing can become a double-edged sword.
He also said TSMC has shifted its internal development model from sequential development to parallel development so technology, manufacturing and customer teams can move at the same time. Customer products may even enter the factory before test vehicle validation is complete, which means many process improvements have to be made in real time during the production cycle.
TSMC will disclose system boundary conditions six quarters before mass production and gather customer feedback, Ho said, so the technology can be aligned with practical needs at the time of validation. He also called on the industry to use the Open Compute Project to build system-level validation standards and best practices, combining early mechanical simulation, later test data and coordinated supply-chain management to speed AI product development and volume ramp.