TSMC validates A16 backside power platform as NVIDIA lines up Feynman on the node
TSMC has completed development and validation of its A16 process platform built with Super Power Rail, or SPR, a backside power delivery network that ETNews said preserves compatibility with existing design ecosystems. The report says TSMC is the first foundry to bring backside power supply technology to the Angstrom-class era while keeping current design infrastructure largely intact, a point that matters for large chip customers already invested in the N2 and N2P ecosystem. According to the report, the move addresses a growing bottleneck in sub-2 nm chip design, where power and signal routing compete for limited front-side space, raising routing congestion and voltage drop risks. TSMC’s SPR architecture shifts power delivery to the back of the chip and uses dedicated backside contacts to feed each transistor’s source and drain, while leaving front-side gate structures, cell size, and layout area nearly unchanged. ETNews said A16 can deliver 8% to 10% higher performance at the same power, or cut power use by 15% to 20% at the same speed, with chip density also rising 8% to 10% versus N2P. The report also said NVIDIA’s next-generation AI accelerator platform, Feynman, will use A16 and aims for mass production in the second half of 2028, alongside large-scale use of CPO and SoIC 3D stacking.








