ChainCatcher reported that semiconductor research firm SemiAnalysis said in an Oct. 15 article that ASML has not officially announced a related product, but patents, media reports and the company’s roadmap all indicate it is developing hybrid bonding equipment.
The article’s author said ASML may launch a more technically challenging chip-to-wafer hybrid bonding tool first, treating it as an extension of vertical integration.
Patents point to a chip-to-wafer focus
According to the patents, the system runs on a track. Each chip is placed on an individual carrier and then moves through inspection, cleaning, plasma activation, topography inspection, leveling, coarse alignment, position adjustment and fine alignment before entering the bonding station. Final placement is handled by the carrier and a vacuum chuck.
The article added that the track system’s repeatability is about 10 microns, well below the roughly 50 nanometers needed for bonding.
ASML filed 27 bonding patent families from December 2022 to November 2024, with most of them targeting chip-to-wafer applications.
Reported design work and existing production use
The Elec reported in March that ASML had started hybrid bonding machine architecture design work with Prodrive Technologies and VDL ETG.
The article said wafer-to-wafer hybrid bonding is already used in image sensors and 3D NAND. Chip-to-wafer bonding, by contrast, is currently used only in logic chip mass production, including AMD’s hybrid-bonded V-Cache shipped since 2022 and TSMC’s SoIC.
SoIC currently has a pitch of about 6 microns, with a target of reaching about 4.5 microns around 2029.
Besi is currently the only supplier with chip-to-wafer mass-production tools, and the related logic business is mainly concentrated at TSMC and Intel.