Jukan, an analyst at Citrini, said in a post on August 30 that Nvidia's Rubin Ultra could see its HBM configuration drop from 12-layer HBM4E to 8-layer, according to his sources. OpenAI and Anthropic had even requested 4-layer parts, but memory makers refused. The downgrade appears likely to stop at 8 layers.
Yield and cost pressure behind the cut
Jukan attributes the change mainly to yield and cost. If Rubin Ultra used 12-layer HBM4E and price increases were factored in, memory costs could reach roughly 70% of Rubin Ultra's total bill of materials. That makes the choice of stack height particularly sensitive.
Software optimization reshapes memory demand
Software optimizations such as model quantization, MLA, and splitting compute tasks are shifting rarely accessed KV cache and model states to LPDDR, CXL, and NAND. HBM is left mainly for the working set required by current computation. As a result, once minimum capacity is satisfied, customers are placing more importance on HBM bandwidth than on capacity.
Fewer layers, bigger HBM demand?
In Jukan's view, reducing the number of stacked layers improves packaging yield, which can increase shipments of both HBM and AI accelerators. That could actually expand total HBM demand. Meanwhile, higher bandwidth requirements reduce the share of chips passing speed binning on a wafer, consuming additional DRAM wafer capacity.
Long-term: memory and logic converge
Looking further out, Jukan sees HBM eventually being replaced by a new architecture, with the likely endgame being the fusion of memory and logic chips. The next two years will be a critical period for memory makers trying to expand into the logic business.