Samsung Electronics has recently created a BEOL process organization within the etching technology team of its memory business, according to Odaily. The company plans to complete the setup this month and begin operations at its Pyeongtaek campus, with an initial headcount of about 30 people. Most of the team members are senior engineers.
The group is discussing BEOL process technology for high-value-added memory products such as HBM, along with staffing arrangements and stronger supply chain operations. BEOL, or back-end-of-line processing, refers to the metal interconnect formation stage that comes after device fabrication on the wafer and is used to connect components and transmit signals.
Samsung began shipping HBM4 in the first half of this year. The product carries 2,048 I/O channels, double the number in the previous generation. Increasing I/O within a limited chip area requires denser wiring and narrower line widths, raising the bar for metal interconnect formation and etching precision. The new organization is still in its early formation stage, and its specific operating direction and targets have yet to be defined.
Samsung Electronics has recently formed a BEOL process organization within the etching technology team of its memory business, according to Odaily. The company plans to complete the setup this month and launch operations at its Pyeongtaek campus, with an initial staff of about 30 people.
The organization is made up largely of senior engineers. Its current discussions cover BEOL process technology for high-value-added memory products such as HBM, staffing plans, and stronger supply chain operations.
Unit to focus on back-end interconnect needs for HBM4
BEOL, short for back-end-of-line, is the metal interconnect formation process in the later stage of semiconductor front-end manufacturing. It is used to connect devices on a wafer after device formation and to transmit signals.
Samsung started shipping HBM4 in the first half of this year. The product has 2,048 I/O channels, double the count of the previous generation.
Adding more I/O within limited chip area requires denser wiring and narrower line widths. That raises the precision requirements for both metal interconnect formation and etching.
The organization is still at an early stage, and its specific operating direction and targets will be clarified later.
This article was originally published by Bit.Fan. For more cryptocurrency news and market insights, visit www.bit.fan. Disclaimer:
The market information, project data, and third-party content displayed on this platform are for industry information sharing only and do not constitute any form of investment advice or return commitment.
Cryptocurrency trading carries high risks. Users should fully assess their risk tolerance and make independent decisions. All profits, losses, and legal responsibilities are borne by the users themselves.
