Competition in next-generation HBM is moving beyond DRAM chip performance and into advanced packaging.
According to a report cited by Damnang on Oct. 7, based on interviews with technical personnel, SK hynix has encountered difficulties in developing hybrid bonding for future HBM, while Samsung Electronics has reportedly started delivering samples using that technology to customers. If that account is later confirmed, Samsung may have gained an early edge in validating advanced packaging for the next wave of HBM.
Still, the information did not come from official statements by either company. It was based on interviews and secondary reporting, and it did not specify the HBM generation, stack count, or customer names involved. That leaves too many gaps to judge the real development distance between the two companies, and it is not enough to conclude that Samsung has already taken a clear overall lead in next-generation HBM.
Just as important, progress in hybrid bonding does not directly map to the overall development pace of SK hynix's next-generation HBM products.
SK hynix is still pushing HBM4E with its current packaging technology
On June 18, SK hynix said it had delivered 12-layer HBM4E samples with 48GB capacity to major customers using its existing Advanced MR-MUF packaging technology. The company said the product improved thermal resistance by 17% compared with HBM4.
That means SK hynix is still advancing next-generation HBM products through its current packaging route even if hybrid bonding development is facing obstacles. The more relevant question now is how far conventional packaging can continue to meet performance, thermal, and package-height requirements as HBM moves to higher stack counts, and what manufacturing barriers hybrid bonding still has to clear before it can scale.
Why hybrid bonding matters for future HBM
HBM stacks multiple DRAM dies vertically to provide high-bandwidth memory for GPUs and AI accelerators. As AI models grow larger, HBM has to raise capacity and bandwidth while keeping power consumption and heat under control inside limited package space.
Today, conventional HBM stacks usually connect upper and lower dies through micro bumps, then use fill and protection materials to handle the gaps between chips. SK hynix's Advanced MR-MUF is one example of that route, relying on optimized micro-bump connections and liquid protective material filling and curing to improve structural reliability and thermal behavior.
Hybrid bonding is designed to reduce reliance on micro bumps. The method directly connects copper interconnect structures on the surfaces of upper and lower dies while bonding the surrounding dielectric layers together, reducing the space taken up by conventional interconnect structures.
The appeal is straightforward. Smaller interconnect pitch and shorter electrical paths can raise interconnect density, reduce signal loss, and create room for denser DRAM stacking. Cutting some of the intermediate materials at the bonding interface may also improve heat transfer.
As HBM moves from 12 layers to 16 layers and beyond, spacing constraints and thermal pressure between chips become more severe. That is where hybrid bonding starts to look more valuable.
Samsung introduced its hybrid copper bonding technology, HCB, on March 17 in materials tied to GTC-related events and positioned it as a solution for next-generation HBM with 16 layers or more. Samsung said HCB could reduce thermal resistance by more than 20% compared with thermocompression bonding, or TCB.
That technical direction lines up with the recent report about sample progress, but a technology presentation is not the same thing as mass production. Samsung's published thermal-resistance improvement also cannot be ranked directly against SK hynix's 17% improvement for HBM4E over the prior generation. The comparison bases are different: one compares bonding methods, the other compares product generations.
The hard part is making the bonding process repeatable
The manufacturing challenge in hybrid bonding goes well beyond aligning and attaching two chips with high precision.
According to process explanations from Applied Materials, chemical mechanical planarization, or CMP, is one of the key steps. Manufacturers have to control the height relationship between copper pads and surrounding dielectric layers with great precision so the bonding surface meets nanometer-level flatness requirements.
If the copper surface is recessed too deeply, the upper and lower copper structures may not make sufficient contact. If it protrudes too much, it can interfere with dielectric bonding and raise the risk of interface defects. Surface flatness, copper pad height, and uniformity across the bonding area all have to be tightly controlled.
At the same time, particles generated during polishing and die singulation, surface contamination, and changes in surface properties after activation can all affect bonding quality. That forces manufacturers to coordinate cleaning, surface treatment, cleanroom conditions, and the bonding time window.
In other words, hybrid bonding is not solved by buying a single high-precision bonding tool. Polishing, cleaning, inspection, die alignment, and bonding have to work as a stable process chain before successful lab bonding can become repeatable production output.
HBM's own structure adds another layer of difficulty. DRAM dies have to become thinner to keep package height under control as stack counts rise. Thinner dies are more vulnerable to mechanical stress and warpage, which increases the risk of misalignment and bonding defects. More layers also mean more bonding interfaces and, with them, more potential failure points.
There is, however, no reliable information showing which exact process step has caused trouble for SK hynix. CMP, contamination, and die warpage are common manufacturing challenges in hybrid bonding, but they cannot be treated as the confirmed reason behind the reported setback.
Yield remains the gate between technical validation and mass production
The industrial path for hybrid bonding also depends on the bonding scheme used.
imec has previously demonstrated wafer-to-wafer bonding, where two wafers are aligned and bonded as complete units. That approach can process a large number of chips at once, but if defective dies are bonded together as well, overall yield may suffer.
Another route is die-to-wafer bonding, where known-good dies are screened first and then placed one by one onto a target wafer for bonding. The advantage is that manufacturers can prioritize tested good dies, but pick-and-place, alignment, and bonding on a die-by-die basis can create throughput challenges.
An interpretation published by the SK hynix Newsroom from Inha University professor Seunghwan Joo said die-to-wafer bonding is moving toward commercial HBM applications. That points to a distinction the market cannot ignore: bonding precision proven at wafer level is not the same issue as the yield and manufacturing efficiency required for multilayer HBM production.
Equipment suppliers are also building out the process chain around this problem.
On Oct. 1, Applied Materials and Besi said they were expanding their cooperation in advanced packaging. The companies are combining Applied Materials' process technologies in polishing, cleaning, and metrology with Besi's die placement and bonding technologies. One result is Kinex, an integrated die-to-wafer hybrid bonding system.
The partnership shows how competition in hybrid bonding is extending beyond the precision of a single tool and toward process integration before and after bonding. Current public information does not show that Samsung or SK hynix has adopted that system.
For HBM manufacturers, the real challenge is to keep every bonding interface stable, maintain product reliability after multilayer stacking, and do so while keeping throughput and manufacturing cost within an acceptable range. A successfully bonded sample is only the first step.
Whether a sample lead becomes a production lead is still an open question
If the report is accurate and Samsung has already delivered hybrid-bonded HBM samples to customers, the immediate advantage would be in R&D timing and customer validation. Entering customer testing earlier can help uncover issues in bonding reliability, thermal behavior, and system integration sooner, giving the company more feedback for later product development.
But there is still a gap between sample delivery and mass production. Customer qualification progress, volume-production yield, manufacturing cost, and supply scale are the metrics that matter when judging whether a technical lead can turn into commercial strength.
At the same time, SK hynix has already moved HBM4E samples forward through Advanced MR-MUF, showing that the conventional packaging route still has room to operate. Hybrid bonding does not mean existing processes disappear overnight. The two routes can develop in parallel, with the eventual choice shaped by performance targets, manufacturing capability, and production economics.
For that reason, one interview-based report is not enough to say Samsung has fully pulled ahead, and difficulties in hybrid bonding should not be treated as proof that SK hynix's HBM product development has stalled.
The next stage to watch is where each company introduces hybrid bonding in terms of HBM generation and stack count, and whether customer qualification, production timelines, and yield begin to show meaningful differences.
HBM competition is shifting from a simple race to increase stack count into a broader contest involving memory design, bonding processes, thermal management, and advanced packaging. Hybrid bonding may unlock more of the potential in dense stacking, but its industrial value will be decided not by whether a batch of samples can be made, but by whether the technology can be turned into stable yield, acceptable cost, and sustained delivery capacity.
Market-share changes are part of the picture as well
The article also pointed to another layer behind the news: Samsung's changing position in the HBM market.
In current HBM shipments led by HBM3E and HBM4, SK hynix remains the leading manufacturer with a 50% market share. The article also said SK hynix's share has edged lower after previously accounting for as much as 64% of global HBM memory spending.
According to Counterpoint Research data cited in the article, Samsung's HBM market share rose from 21% in the first quarter to 33% in the second quarter, while SK hynix's share was pulled to 30%. The article said that share could expand further as HBM4 shipments increase in the second half.
It also cited market expectations that by 2027, Samsung's HBM product pricing will be more than double this year's level, with contract prices the highest among the three major memory manufacturers, including SK hynix and Micron. Data from KB Securities said HBM4's share of Samsung's HBM sales is expected to double from 40% this year to 80% by 2027.
Based on those figures, the original article argued that Samsung appears to be staging a notable comeback in HBM.
The piece was sourced from the WeChat public account "Semiconductor Industry Observation" (ID: icbank) and credited to its editorial team.