NVIDIA has already moved into development and supply-chain planning for Feynman, the AI accelerator platform expected to follow Rubin, according to a Digitimes report cited by ABMedia. The report says Feynman is set to use TSMC’s upgraded A16 process, pair it with custom HBM, and adopt both SoIC 3D stacking and co-packaged optics, or CPO, at scale, with volume production targeted for the second half of 2028. What makes the platform notable is the simultaneous push across three technical layers: process technology, advanced packaging, and optical interconnect. Supply-chain data cited in the report shows NVLink bandwidth rising from about 130 TB/s in Blackwell NVL72 racks to 260 TB/s in Rubin, 520 TB/s in Rubin Ultra, and more than 1,000 TB/s in Feynman. At that level, copper links are approaching practical limits in distance, power, signal loss, and thermal management, making optical interconnect a more direct fit for large AI clusters. The same report says TSMC is expanding advanced packaging capacity from AP5 and AP6 into AP7 and AP8, while repeatedly lifting SoIC monthly capacity targets from 20,000 wafers by the end of 2026 to 50,000 by the end of 2027. It also places Feynman inside NVIDIA’s wider capital and supply strategy, including more than $40 billion invested across the AI ecosystem since 2026 and a financing platform with Apollo, BlackRock, Blackstone, and Goldman Sachs aimed at mobilizing $500 billion in third-party capital.

Taiwan Semiconductor Manufacturing Co. is accelerating work on its CoPoS and COUPE silicon photonics technologies, while AUO-linked companies Epistar, Tyntek and LandMark Optoelectronics are assembling around the co-packaged optics, or CPO, theme, according to ABMedia. The report says the group is positioning itself across light emission, sensing and packaging as suppliers look for an early foothold in next-generation advanced packaging led by TSMC. ABMedia describes CoPoS as a packaging approach that replaces the traditional silicon interposer with a very large glass substrate, expanding the area available for integrating multiple high-performance GPUs and ASICs into a single package. But the report also notes that higher chip density intensifies heat and power problems in ultra-high-compute environments, where conventional electrical transmission and copper interconnects are approaching physical limits. Against that backdrop, CPO is being framed as a route to move part of the interconnect from electrical to optical signaling by integrating optical transceivers directly into the package. Economic Daily News, cited in the report, says AUO is handling packaging integration and testing, while Epistar, Tyntek and LandMark each focus on different optical components. Market observers cited by ABMedia expect the group’s validation work to convert into orders and revenue as TSMC’s CoPoS ecosystem moves toward volume ramp-up.

NVIDIA Senior Vice President Gilad Shainer said at a recent technical forum that co-packaged optics, or CPO, has formally entered mass production, adding that the biggest future growth driver for optical communications will come from scale-up architectures, where bandwidth demand is more than 10 times that of scale-out systems. He said switches developed jointly by NVIDIA and its supply-chain partners have already been delivered to close partners and deployed inside NVIDIA’s own facilities, with a larger rollout to AI factories around the world expected this year. The remarks triggered a sharp move in Taiwan’s optical communications names. ABMedia reported that Lianya, Accton, Browave, GCS, LuxNet, and Alpha Networks-related peers were among the shares that surged, with several hitting limit-up. The report also cited TrendForce, which estimates the CPO/NPO market could exceed $39 billion by 2030, though the firm expects the real growth curve to emerge only after late 2027 and accelerate in 2028 and 2029. ABMedia noted that Shainer’s comments were not entirely new. The publication said they were a public response to a bearish SemiAnalysis report from several months ago rather than a fresh disclosure. The article also drew a distinction between announcing mass production and reaching shipment volumes large enough to make a meaningful revenue contribution, with multiple research houses placing large-scale deployment no earlier than late 2028 or early 2029.

X platform analyst Serenity named AAOI, SIVE, FOCI, and Shunsin Technology as top AI photonics picks, with X-FAB as an alternate, based on key positions in the optical communications and CPO supply chain.

According to Odaily, people familiar with the matter said NVIDIA has decided, for now, not to adopt Taiwan Semiconductor Manufacturing Co.'s COUPE technology route. The company’s earlier “Plan A” was built on TSMC’s co-packaged optics platform and used 8-wavelength dense wavelength division multiplexing, or DWDM, along with roughly 50 to 64G NRZ modulation. NVIDIA’s latest “Plan B” instead moves to Tower Semiconductor’s silicon photonics platform. That setup uses 16-wavelength DWDM and 200G/400G PAM4 modulation, marking a clear change in the optical packaging and transmission approach described in the report. No additional timeline or reason for the switch was disclosed in the source item.

Citrini analyst Jukan said on X on July 12 that Nvidia has decided, at least for now, not to adopt Taiwan Semiconductor Manufacturing Co.'s COUPE, or Compact Universal Photonic Engine, technology route. He attributed the move to slow progress in TSMC's silicon nitride, or SiN, development and weaker-than-expected work on a 2D grating coupler. According to Jukan, Nvidia's earlier "Plan A" had been built around TSMC's co-packaged optics platform based on COUPE. The latest "Plan B," he said, shifts to a silicon photonics platform from Tower Semiconductor. Jukan had also previously said that the release timing for Nvidia's next-generation Rubin architecture products could be pushed back again. The post did not include any additional timeline or product details beyond those points.