Two-dimensional semiconductors, often described as atomically thin semiconductors, have active layers only one atom or a few atoms thick. Representative materials include transition metal dichalcogenides such as molybdenum disulfide. As silicon-based chipmaking approaches physical limits, conventional silicon channel materials are nearing their performance ceiling. Materials such as MoS2, WSe2, and indium selenide are increasingly seen as strong candidates for the post-Moore era because their atomic-scale thickness gives them natural electrostatic control at short channel lengths.
A broader industry consensus is now forming around that view. The article says major chipmakers including Taiwan Semiconductor Manufacturing Co. (TSMC), Intel, and Samsung, along with research organizations such as imec and IRDS, have all moved into the 2D semiconductor field and expect these materials to become core components in heterogeneous integration after the 1 nm node. In June 2026, TSMC, ASML, and imec presented integrated 2D n/pFETs on a 300 mm wafer with a 50 nm contacted gate pitch at the VLSI symposium, a step the article describes as a sign that large manufacturers are pushing 2D transistors out of the lab and toward production lines. China’s domestic supply chain, it says, is also moving across the stack, from material growth and equipment development to chip integration and ecosystem building.
Materials and equipment are moving from proof of concept to production
For 2D semiconductors to reach industrial use, large-scale and high-quality wafer production is essential. Chemical vapor deposition, or CVD, and metal-organic chemical vapor deposition, or MOCVD, are presented as the key methods for manufacturing these materials at scale.
In equipment and material growth, a team led by Professor Wang Xinran of Nanjing University and its commercialization platform Jimo Core Technology has built what the article calls a closed loop linking academic innovation, equipment development, and process verification. In October 2025, using the self-developed Oxy-MOCVD 200 ultra system, whose core components were said to be 100% domestically produced, the team reported what it described as the world’s first mass-producible 6-inch single-crystal wafer of a 2D transition metal dichalcogenide semiconductor. The process is compatible with materials including MoS2, WS2, and WSe2, and delivered a unidirectional domain alignment rate above 99% on 150 mm wafers.
In January 2026, Wang’s team and a group led by Wang Jinlan at Southeast University developed an oxygen-assisted MOCVD, or oxy-MOCVD, process. According to the article, that technique pushed the average MoS2 domain size from the hundred-nanometer scale to several hundred micrometers, addressed the challenge of large-area uniform growth, and suppressed carbon contamination at the source. Jimo Core then upgraded its equipment around that process and says it can now provide plug-and-play process capability for downstream users across mainstream 2D semiconductor materials including MoS2, MoSe2, WS2, and WSe2.
The article adds that Jimo Core later became the first company to achieve mass production of 8-inch 2D semiconductor single crystals. Its products have entered research institutions including the University of Cambridge and Fudan University, while the company has also reached cooperation agreements with downstream chip manufacturers, extending the path from lab samples to production-line materials.
Another long-standing bottleneck involved p-type materials. As with silicon CMOS, wafer-scale n-type and p-type 2D semiconductor single crystals are both required to build 2D CMOS integrated circuits. Researchers had already developed several n-type 2D semiconductors, and wafer-scale single-crystal growth had been achieved for materials such as MoS2 and WS2. But p-type materials with both high mobility and good stability remained scarce, and growing them as wafer-scale single crystals was even harder. In July 2026, a team at the Institute of Metal Research, Chinese Academy of Sciences, reported a large-area, high-performance p-type monolayer single-crystal wafer of MoSi₂N₄. The article says the material system was originally created by that team. Earlier work had been limited to polycrystalline thin films, where grain-boundary gaps sharply reduced device performance and created transfer-related damage. This time, a step-guided effect from a special single-crystal substrate enabled directional growth and seamless stitching, filling what the article describes as a critical gap in high-quality p-type materials for 2D CMOS circuits.
In specialty materials, a team led by Professor Peng Hailin at Peking University reported wafer-scale controllable preparation of ultrathin and uniform ferroelectric films and related heterostructures. The team built a high-speed ferroelectric transistor with an operating voltage of 0.8 V and endurance above 1.5×1012 cycles. The article says its overall performance surpassed current industrial hafnium-based ferroelectric systems and represented an international first for a high-performance wafer-scale 2D ferroelectric material platform, creating a new materials route for energy-efficient advanced chips.
An engineering ecosystem is forming around an 8-inch line and a PDK
Breakthroughs in materials and devices still have to be translated into a standardized manufacturing system. That is where process lines, foundry capability, and design tools begin to matter.
On July 9, 2026, the 8-inch 2D semiconductor engineering demonstration process line built by Yuanji Micro Technology was fully connected in Pudong. The article frames this as a milestone for taking 2D semiconductors in China from research into industrialization. The line was first powered up in January 2026 and, after more than half a year of equipment commissioning and process optimization, now supports full tape-out and engineering pilot production. Unlike small experimental platforms in university labs, the line is described as a complete engineering chain spanning material preparation through chip integration.
Before that, the article says, most domestic work in 2D semiconductors was concentrated in university laboratories, with device fabrication largely done through low-volume manual prototyping that remained far from industrial standards. Yuanji Micro spent 10 years working through the full process path, from wafer growth and integration technology to device modeling, circuit design, packaging, and testing.
A process design kit arrived alongside the line. Yuanji Micro released version 0.1 of a 500 nm PDK built on the 8-inch pilot line. The article describes it as the first process IP in the 2D semiconductor field that is compatible with mainstream EDA toolchains. It includes Pcell, DRC, LVS, and PEX tools, reports process yield above 99.99%, and says performance indicators have broken international records while approaching comparable silicon process levels. The kit is expected to support the design and wafer-scale manufacturing of 2D circuits at the 100,000-transistor level.
With the process line and PDK in place, foundry service and ecosystem partnerships are also beginning to open up. Teams from Peking University, Tsinghua University, Shanghai Jiao Tong University, and Nanjing University have signed university-enterprise R&D agreements with Yuanji Micro, and wafer foundry services are now open to research users. Xi’an XianDao Institute and Shanghai 2D Star Technology have also reached strategic cooperation agreements around platform sharing, commercialization, and ecosystem development.
Local industrial support is developing in parallel. According to the article, Chuansha New Town in Shanghai is using Yuanji Micro’s pilot line as a core platform to draw upstream and downstream companies into the area. At the city level, Shanghai has included 2D semiconductors among its future industries for focused cultivation, with the stated goal of forming a full loop covering research, pilot production, and mass manufacturing. The article also notes that roughly 70% of existing silicon semiconductor equipment can be reused for 2D semiconductor production lines, meaning the technology would not overturn the current industrial system but could create new market demand in materials, equipment, manufacturing, and advanced packaging.
Applications are expanding from logic into memory
As manufacturing matures, the application map for 2D semiconductors is extending from logic computation into memory and other use cases.
In logic, Chinese teams have progressed from single devices to complex processors. In 2025, the world’s first 32-bit RISC-V microprocessor based on a 2D semiconductor material, called “Wuji,” was released. It used MoS2, integrated 5,900 transistors, and had a thickness of just 0.7 nm. The article reports a single-stage inverter yield of 99.77% and says the program achieved end-to-end domestic development from material and architecture to tape-out. At a 1 kHz clock frequency, the processor could serially execute 37 kinds of 32-bit RISC-V instructions and satisfied the RV32I integer instruction set. It also offered high single-stage gain and ultra-low off-state leakage, making it suitable for internet-of-things and edge computing scenarios.
In 2026, teams led by Wang Xinran and Qiu Hao at Nanjing University, working with Suzhou Laboratory and Huawei, pushed farther by establishing a full design-process-manufacturing flow for Fab-compatible 2D semiconductor chips. They produced a MoS2 multi-bit parallel microprocessor called MAGIC-1000. The article says the chip set a new record for transistor integration density in emerging non-silicon digital circuits. Built on a 0.5 μm industrial process, the team integrated 1,433 MoS2 transistors into a very compact die area, reaching 9,336 transistors per mm², one order of magnitude above the previous international record and comparable to mature silicon technology at the same node. The chip uses a RISC instruction set and contains four main blocks: an instruction decoder, a register file, an arithmetic logic unit, and a multiplexer. It was the first 2D semiconductor chip to realize multi-bit parallel data computing, with a top operating frequency of 43 kHz, and it integrated an on-chip register file to avoid the latency and bandwidth bottleneck of off-chip storage.
In memory, the ultra-low leakage characteristics of 2D semiconductors are shown as strategically important. A Fudan University joint team developed what the article calls the lowest-leakage 2D semiconductor transistor to date, reaching a level equivalent to just one electron leaking every 9.15 seconds. Based on that device, the team built a new DRAM chip that achieved data retention of more than 8,500 seconds at zero hold voltage, while also supporting high-speed read and write operations and multi-level storage. The optimized capacitorless dual-transistor DRAM, or 2T0C DRAM, achieved quasi-non-volatile operation, 5-bit storage precision, and nanosecond write speed.
Yuanji Micro has identified DRAM as a key strategic direction. The article argues that the ultra-low leakage of 2D semiconductors could sharply reduce refresh power and make the technology suitable first for edge-side and high-compute scenarios, before later scaling DRAM capacity through 3D stacking. In July 2026, a Fudan team led by Zhou Peng and Liu Chunsen went further and clearly observed non-volatile single-electron storage behavior at room temperature for the first time. The team built a device that the article says has the world’s largest non-volatile quantum storage window, with a storage window of 0.5 V created by injecting just one electron.
Beyond computing and memory, 2D semiconductors are also described as offering unique advantages in specialty scenarios. The article characterizes them as extreme SOI materials suitable for radio-frequency analog circuits, radiation-resistant communications, and brain-computer interfaces. In January this year, using the “Fudan-1” satellite platform, a radiation-resistant RF communication system based on 2D semiconductors completed in-orbit space validation for the first time. The materials can also be made into flexible and transparent devices, supporting work in optoelectronic sensing and quantum computing.
The industry chain is broadening
The article concludes that 2D semiconductors in China have moved decisively beyond the laboratory and into engineering verification and small-batch tape-out. From wafer-scale material breakthroughs to engineering process lines and expanding applications in computing and storage, progress is now appearing across the chain. What is taking shape, according to the article, is an emerging industrial system covering materials, equipment, manufacturing, design, and applications.
This article was originally published on the WeChat account “Semiconductor Industry Review” and written by Peng Cheng. MarsBit carried the piece.