ChangXin Memory Technologies (CXMT) is reported to be posting a 25% yield on HBM3, according to a Sept. 9 report by The Chosun Daily cited by Chip Briefing. Based on an eight-layer HBM3 stack, the report said nearly 80 out of every 100 units fail final testing.
Front-end and back-end figures point to a 25% overall yield
The report laid out the number in two parts. Yield in the front-end process was said to be around 30%. Of the products that made it to back-end packaging and testing, only about 70% passed final inspection. Taken together, that puts the overall yield at about 25%.
In the industry, 80% is commonly treated as the benchmark yield for mass production. On that basis, 25% is roughly one-third of that level.
Report contrasts the figure with SK hynix
The report used a South Korean peer as a comparison point. It said SK hynix has kept HBM3 yields above 90% since starting mass production in 2022.
It attributed the gap to the maturity of through-silicon via technology. TSV is a core process in stacking multiple DRAM layers and creates vertical electrical connections between chips. As the number of layers rises, alignment precision and hole quality become more demanding.
Numbers came from an unnamed equipment industry executive
The figures were not released by CXMT. The Chosun Daily cited an unnamed senior semiconductor equipment industry executive described as familiar with CXMT’s situation, while CXMT itself has not published HBM3 yield data.
ABMedia also noted that Chain News had previously reported CXMT disclosed progress on LPDDR6 mass production and domestic DUV at an earnings briefing, and market views on its pace of technical catch-up had been broadly positive. The yield report points in the opposite direction on that metric.