TSMC’s CoWoS advanced packaging line has become one of the tightest constraints in the AI hardware supply chain. The source article says lead times have stretched to 52 to 78 weeks, while capacity utilization has stayed around 95% to 98%. The supply-demand gap is estimated at about 20%. Orders from NVIDIA, Google, and Amazon are already full, and even with monthly CoWoS capacity rising to 140,000 wafers by the end of 2026, demand would still outpace supply.
The pressure is tied to physics as much as demand. According to the report, NVIDIA’s next-generation Rubin GPU has a reticle area reaching 5.5 times the current specification. On a 12-inch circular wafer, that size allows at most seven sets, and practical yield considerations can cut that number down to only four.
Circular wafers are wasting more space as AI dies get larger
CoWoS, short for Chip on Wafer on Substrate, packages compute dies and memory dies together on a circular interposer before assembling the final AI chip. The interposer acts as a high-precision bridge for high-speed communication between chips. It is made of silicon, and reticle size limits make it difficult to scale much further.
As die sizes increase, the unused edge area on a round wafer also grows. The article notes that if next-generation GPUs keep the current structure, the number of good packaged units from a single wafer may fall to single digits. Heat adds another problem. High-power AI chips running for long periods generate large amounts of thermal energy, and the different thermal expansion rates of the chip, interposer, and substrate can cause warpage after cooling, cutting packaging yield.
CoPoS shifts to rectangular panels and could multiply output per material unit
TSMC’s proposed answer is CoPoS, or Chip on Panel on Substrate. Instead of using a circular wafer as the interposer carrier, it moves to a rectangular panel format. In the near term, the company is focusing on a 310 by 310 millimeter substrate.
The main gain is area efficiency. Based on the estimates cited in the article, a flagship AI chip packaged on a circular wafer would yield only 4 sets, while a rectangular panel could produce roughly 9 to 16 sets. That means output per comparable material area could rise by 2 to 4 times. In effect, packaging throughput could increase sharply without a matching increase in equipment count.
The change is not simple. The report says stress tends to concentrate at the four corners of square panels during processing, and uneven thermal expansion can raise the risk of substrate deformation. If process control is not stable enough, yields may fail to improve and could even weaken.
Glass substrates are the longer-term goal, but mass production is still years away
The longer-term roadmap for CoPoS is to replace silicon interposers with glass substrates. The article describes glass as offering a flatter surface and larger area, while also avoiding the reticle-size ceiling that constrains silicon wafers. It also points to lower signal loss and the ability to support more stacked memory layers and larger compute dies.
On TSMC’s roadmap, by 2029 the reticle multiplier could reach 14x, compute performance could improve by 48x, and a single package could hold 24 HBM5E stacks. Still, the material brings clear manufacturing risk. Glass is hard, brittle, and sensitive to thermal shock, and a crack during large-area processing can scrap an entire panel.
On timing, the source says TSMC started building an R&D line at its subsidiary VisEra in 2025. 2026 is described as the key year for material and equipment validation, with the earliest validation completion in June. Trial production is planned for 2027, followed by formal mass production in the second half of 2028 through 2029. Large-scale CoPoS shipments, based on that schedule, are still at least several years away.