High Bandwidth Memory is no longer being framed as a standalone memory problem. At Hot Chips 2026, Samsung and SK Hynix both argued that GPUs, memory, foundry processes and packaging now have to be designed as one system, but the two companies outlined sharply different routes. Samsung is trying to turn the HBM base die from a passive bridge into an active logic layer, moving the memory controller off the GPU, adding memory expansion and selective compute to the base die, and ultimately aiming for zHBM, a structure that vertically stacks DRAM directly on top of compute silicon. Samsung said that approach could free up 5% to 10% of GPU area, lift performance by 10% to 20%, cut DRAM power by about 70%, and deliver more than 2.3x the bandwidth of HBM4E. SK Hynix, by contrast, is concentrating on higher stack counts and the thermal and warpage penalties that come with them. The company said 12-high HBM4 is in production and 16-high parts are in customer validation, while hybrid bonding remains in R&D for 20-high and above. It also presented iHBM, a thermal path built into the hottest region of the stack. Micron took a third angle, arguing that the AI memory wall is widening as accelerator compute rises faster than attached-memory bandwidth, forcing increasingly difficult trade-offs across bandwidth, capacity, packaging complexity, heat and reliability.

SK hynix and SanDisk introduced the first HBF specification at the 2026 FMS Conference in Santa Clara, California. The first version targets up to 512GB of capacity and bandwidth ranging from 0.4 TB/s to 3.0 TB/s, with UCIe used as the interconnect between HBF and the processor. SanDisk also showed a test case suggesting that, in a specific AI inference setup, four GPUs paired with 4TB of HBF delivered nearly the same token output per second as eight GPUs paired with 192GB of HBM. The companies are positioning HBF as a new memory tier between HBM and conventional NAND storage. SK hynix also outlined a revised memory hierarchy that adds G0.5, G1.5 and G2.5 tiers, while SanDisk said HBF is meant to support persistent KV cache and other large inference-state data. The roadmap now points to a full HBF specification in early 2027 and samples in early 2028.

A MarsBit report argues that AI agents are changing storage from a passive persistence layer into part of the execution path itself. As agents continuously observe, reason, call tools, write back results and preserve state, the value of storage is no longer limited to saving data after a task is complete. The report says SSDs are beginning to take on functions tied to model weights, KV cache spillover, indexing, encryption, compression, lifecycle control and long-term memory, pointing to a broader shift toward programmable, functional SSDs. The piece lays out how this transition could play out on both devices and in the cloud. On the edge, SSDs may become the long-lived state layer for personal agents, holding local models, adapters, vector indexes, personal memory and tool traces. In cloud deployments, storage nodes could move closer to the inference path, handling shared prefixes, KV data, adapters, vector search and governance. The report cites Mooncake and NVIDIA CMX as examples of systems where storage is already participating in token production rather than merely holding cold data. It also argues that the rise of agent systems does not diminish HBM. Instead, HBM, HBF, DRAM/CXL and SSDs are likely to be re-tiered by speed, mutability, capacity, cost and governance needs. Existing AI SSD efforts from Phison, Longsys, Maxio and partners are presented as early industrial samples of this shift, where the focus is moving from faster disks for AI workloads to a reallocation of responsibilities across runtime, memory hierarchy, controllers and flash.

A PANews analysis argues that August 4, 2026 marked a turning point for the memory industry. On the same day, SK hynix and SanDisk introduced the first standard for high-bandwidth flash, or HBF, at FMS 2026, while TrendForce reported that Nvidia was evaluating lower HBM configurations for Rubin Ultra. The article says those two developments point in the same direction: the core constraint in AI infrastructure is shifting away from on-package memory alone and toward interconnects across chips, packages, racks, and systems. The piece traces that shift through Nvidia’s Vera Rubin launch, NVLink 6 bandwidth gains, Spectrum-X CPO shipments, Intel’s EMIB-T packaging push, TSMC’s reported work on an EMIB-like approach, and the emergence of UCIe-linked memory tiers such as HBF. In that framework, optical and electrical interconnects sit at the top of the stack, advanced packaging becomes the physical foundation, HBM remains essential but less open-ended from an investment perspective, HBF represents a new category aimed at inference-era capacity pressure, and CXL memory pooling remains an option for later years. Rather than framing this as a broad “memory bull market,” the article’s main point is that value inside the storage empire is being redistributed as the bottleneck migrates.

WhiteLine Daily said the launch of a public HBF specification matters because it turns the concept from a single-company proposal into a shared industry standard. SK hynix and SanDisk published the first HBF technical specification through the Open Compute Project, defining 8-layer and 16-layer NAND stacks, capacities of up to 512GB per package, bandwidth tiers of roughly 0.4 TB/s to 3.0 TB/s, and UCIe connectivity to CPUs, GPUs and other accelerators. Google and Tenstorrent have also joined the HBF consortium. The report argues that HBF is not meant to replace HBM. Instead, it adds a new memory tier between HBM and SSD, placing larger-capacity storage closer to xPU compute. High-frequency, latency-sensitive data would still remain in HBM or DRAM, while model weights with lower access frequency could sit in HBF. That setup may be especially relevant for MoE models, where many expert weights stay idle most of the time yet still consume capacity. WhiteLine Daily said the short-term investment angle is still not HBF revenue, since first HBF samples are scheduled for the second half of 2026 and the first inference device samples using HBF are expected in early 2027. The nearer catalysts are SanDisk’s earnings, NAND pricing, data center demand, margins, customer agreements, and enterprise SSD progress.

SK hynix said at FMS 2026 that it has jointly released the first High Bandwidth Flash, or HBF, standard specification with Sandisk, roughly six months after the two companies formed the alliance in February this year. The specification has been disclosed through the Open Compute Project and sets out key parameters including capacities of up to 512GB, three bandwidth tiers topping out at about 3.0TB/s, and use of the UCIe interconnect interface. Google and Tenstorrent have confirmed they are joining the HBF alliance. The technology is positioned as a new storage tier between high-bandwidth memory and SSDs, combining HBM-class transfer speeds with NAND’s larger capacity scaling. During the event, SK hynix also publicly showed its 10th-generation V10 375-layer 4D NAND wafer and related product for the first time, saying energy efficiency is 2.5 times better than the previous generation and that mass production is expected early next year. In a conference presentation, an SK hynix executive also outlined a tiered memory architecture as a way to address data-processing demands in the AI inference era.