Chinese memory makers Yangtze Memory Technologies Co. (YMTC) and ChangXin Memory Technologies (CXMT) are stepping up overseas efforts under geopolitical pressure and export controls, with North America emerging as a key target. DigiTimes reported that YMTC has been selling NAND chips to independent module makers, which then assemble them into enterprise solid-state drives and ship the products to several U.S. neocloud providers. The arrangement is described as a way to blur the products’ Chinese origin before they reach end customers. The report also said U.S. private companies are, in principle, still allowed to buy products from YMTC and CXMT under current rules, although they are expected to assess related risks carefully. On the production side, YMTC’s Phase 3 Wuhan fab has reportedly been moved up from the second quarter of 2027 to the fourth quarter of 2026, with monthly capacity set at 100,000 wafers and an initial 50,000-wafer ramp. About 20% of that capacity is planned for LPDDR trial production, marking YMTC’s first move into DRAM. CXMT, meanwhile, has started qualification work with small and mid-sized cloud service providers in the U.S. and Canada as DDR5 and LPDDR5 supply tightens. Supply-chain sources cited in the report also projected that China’s memory self-sufficiency could surpass 50% between late 2027 and 2028.

Apple is actively exploring the addition of Chinese memory makers ChangXin Memory Technologies and Yangtze Memory Technologies Co. to its supply chain, according to a DIGITIMES report cited by ChainCatcher. The report says both companies are continuing to expand and are drawing attention over whether they can formally enter Apple’s supplier system. Industry sources quoted in the report said the two manufacturers are using Apple as a benchmark to demonstrate that Chinese DRAM and NAND Flash products have reached international quality standards, while also shipping to North American neocloud and enterprise customers through third-party assembly channels. The report also details their capital plans and production ramp-up. CXMT’s parent company has completed a 29.5 billion yuan fundraising round, while YMTC is preparing an IPO expected to raise about 33 billion yuan for production-line upgrades and research and development. DIGITIMES added that YMTC turned profitable in 2024, posted 33.379 billion yuan in attributable net profit in the first quarter of 2026, and plans to bring its phase-three plant online in the fourth quarter of 2026.

Xiaomi on Monday introduced its in-house flagship smartphone chip, the Xring O3, built on a 3nm process and manufactured by Taiwan Semiconductor Manufacturing Co. The launch marks a deeper push into self-developed silicon after the company’s 2025 Xring O1, and puts fresh pressure on long-time suppliers Qualcomm and MediaTek in the high-end mobile SoC market. According to Xiaomi, the Xring O3 delivers more power-efficient imaging and stronger on-device AI computing. The company also released the Xring O100 and D100 alongside it. Specifications disclosed in the report show a 133 sq mm die with more than 24 billion transistors, LPDDR6 support, 113.8GB/s memory bandwidth, a 10-core CPU, and a 16-core G2-Ultra NX GPU. Xiaomi said multi-core performance improved about 60% from the previous generation, while GPU performance rose as much as 85% and energy efficiency improved 64%. Still, Bloomberg Intelligence analysts Steven Tseng and Rebecca Wang said the chip’s reported shipment target of only 200,000 to 300,000 units suggests Xiaomi remains far from replacing Qualcomm and MediaTek at scale. The first phone to use the chip will be the Xiaomi 18 Fold, scheduled for release in September 2026.

NVIDIA has released its first silicon test results for the Vera Rubin NVL72 rack, using DeepSeek-V4-Pro in a coding-focused agent workload rather than a conventional fixed-length inference benchmark. According to the company, Vera Rubin NVL72 delivered up to 30x higher throughput per megawatt than GB300 NVL72 under the AgentX benchmark, while the cost to produce one million tokens fell by as much as 35x. The test framework came from SemiAnalysis and was built to replay full coding sessions with growing context, tool use, and sub-agent generation, reflecting how agent systems behave in production. The company also disclosed that Groq 3 LPX has entered full production as a low-latency inference extension for the Vera Rubin platform. In an Artificial Analysis benchmark, Groq 3 LPX ran Gemma 4 31B with a 100,000-token context window at 3,400 tokens per second, and its peak output in coding workloads reached 6,981 tokens per second. NVIDIA said Vera CPU, a processor built for agent workloads with 88 Olympus cores and 1.2 TB/s of LPDDR5X bandwidth, is also moving into deployment, with SpaceXAI named among early adopters.

Ingenic rang the opening bell in Hong Kong on Aug. 25, debuting at HK$100 per H share and reaching an opening market capitalization of about HK$51.5 billion. The company had already been listed on Shenzhen’s ChiNext board since May 31, 2011, and the new listing places it among semiconductor companies with both A-share and H-share listings. The prospectus outlines a chip platform strategy built across three product lines: memory, compute and analog. That structure took shape after Ingenic completed its acquisition of Beijing Silicon and indirectly took control of Integrated Silicon Solution Inc. (ISSI) in 2020. Since then, the company has operated around three brands: ISSI for memory, Ingenic for compute and Lumissil for analog. Its recent numbers show a rebound. Revenue moved from RMB 45.31 billion in 2023 to RMB 42.13 billion in 2024, then back up to RMB 47.41 billion in 2025. First-quarter 2026 revenue reached RMB 15.60 billion, up 47.1% from a year earlier, while net profit rose to RMB 3.20 billion and gross margin climbed to 42.6%. Ingenic said it expects to raise HK$3.13 billion from the Hong Kong offering. Half of the proceeds are earmarked for R&D, while 25% is set aside for strategic investments and acquisitions.

High Bandwidth Memory is no longer being framed as a standalone memory problem. At Hot Chips 2026, Samsung and SK Hynix both argued that GPUs, memory, foundry processes and packaging now have to be designed as one system, but the two companies outlined sharply different routes. Samsung is trying to turn the HBM base die from a passive bridge into an active logic layer, moving the memory controller off the GPU, adding memory expansion and selective compute to the base die, and ultimately aiming for zHBM, a structure that vertically stacks DRAM directly on top of compute silicon. Samsung said that approach could free up 5% to 10% of GPU area, lift performance by 10% to 20%, cut DRAM power by about 70%, and deliver more than 2.3x the bandwidth of HBM4E. SK Hynix, by contrast, is concentrating on higher stack counts and the thermal and warpage penalties that come with them. The company said 12-high HBM4 is in production and 16-high parts are in customer validation, while hybrid bonding remains in R&D for 20-high and above. It also presented iHBM, a thermal path built into the hottest region of the stack. Micron took a third angle, arguing that the AI memory wall is widening as accelerator compute rises faster than attached-memory bandwidth, forcing increasingly difficult trade-offs across bandwidth, capacity, packaging complexity, heat and reliability.

Nvidia said on Aug. 24 that SpaceXAI will deploy its Vera CPU to speed up next-generation agentic AI applications. Vera is the first CPU built specifically for AI agents, according to Nvidia, and it features 88 in-house Olympus cores, spatial multithreading and LPDDR5X memory with bandwidth of 1.2 TB/s. Nvidia said the chip can deliver up to 1.8 times faster task completion than x86 CPUs in agentic AI, reinforcement learning and data processing workloads. SpaceXAI President Mike Nicolls said Vera’s CPU performance and memory bandwidth are enough to support large-scale task orchestration, code execution and data processing while keeping GPUs running efficiently. SpaceXAI also plans to expand the AI infrastructure behind Grok using Nvidia’s Vera Rubin platform and move toward gigawatt-scale compute capacity. Vera Rubin combines Nvidia accelerated computing, NVLink interconnect, Spectrum-X networking and BlueField data processing technology, with the goal of lowering per-token cost and improving overall AI factory efficiency. Nvidia also said SpaceXAI will send an optimized Vera Rubin NVL72 system into space, where the first-generation Starmind AI satellite will use the rack-scale architecture. Nvidia described that as its first landmark deployment extending accelerated computing from terrestrial data centers to orbital computing.

Xiaomi founder Lei Jun said the company’s new Xring chip lineup — Xring O3, Xring O100 and Xring D100 — has completed tape-out validation, according to ChainCatcher. The flagship Xring O3, described as an AI SoC for Xiaomi’s highest-end products, is set to make its debut in the Xiaomi 18 Fold. Xring O100, a high-bandwidth AI accelerator, and Xring D100, described as China’s first 3nm high-compute AI chip for smart driving, are scheduled for commercial use next year. Xiaomi disclosed a detailed set of specifications for O3. The chip uses a 3nm process, measures 133 mm², carries 24 billion transistors, and posts an AnTuTu extreme benchmark score of 5.22 million. Its CPU uses a 10-core all-big-core design with a top frequency of 4.35 GHz, while Geekbench scores were listed at 3,945 for single-core and above 15,000 for multi-core. The GPU has 16 cores, supports ray tracing, and was said to deliver major graphics gains over the previous generation while cutting power consumption by 64%. The company also said O3 is the first in the industry to support LPDDR6 and offers 200 TOPS of NPU Tensor compute, with dedicated optimization for large language model inference. Xiaomi added that it has spent more than five years on renewed large-chip development, investing more than RMB 21 billion and building a chip team of nearly 3,000 people.