Chinese DRAM maker ChangXin Memory Technologies, or CXMT, has started pilot production of fourth-generation high-bandwidth memory HBM3, with initial yields stalled at 25%, according to a report by The Chosun Daily cited by ChainCatcher. The report said that level is roughly one-third of the 80% yield often seen as a target for mass production. SK Hynix has been mass-producing similar products since 2022, with yields above 90%. For CXMT’s 8-layer HBM3 stack, front-end process yields were reported at about 30%, while roughly 70% made it through the back-end process as final good units. The company has supplied a small number of samples to Chinese firms including Alibaba’s T-Head and Cambricon, and is continuing to improve yields. The report added that CXMT’s G4, a 17nm-class process, does not face major issues in conventional DRAM production, but HBM requires larger DRAM die and tighter electrical specifications. Industry sources in the report pointed to limited maturity in through-silicon via, or TSV, technology. Analysis from Nomad Semi said Samsung’s HBM2 has more than 5,000 TSVs per chip, SK Hynix’s HBM3 has more than 8,000, and CXMT has about 3,000, leaving the company 4 to 5 years behind Samsung and SK Hynix.

TrendForce's latest research reveals that the global DRAM industry revenue reached approximately $154.73 billion in Q2 2026, rising 59.5% quarter-over-quarter, driven by AI server demand for HBM3e, LPDDR5X, and high-capacity RDIMM. Supply growth remains constrained as manufacturers prioritize server allocation, with bit shipments expanding only modestly, signaling that AI demand continues to exceed supply expansion.

A research note from Schulz_Research said China’s memory buildout is no longer centered on a single company, but on a three-part structure led by CXMT, YMTC and XMC. In the note, CXMT is described as handling DRAM wafers, while YMTC focuses on NAND and is adding DRAM at its newest plant. XMC, a foundry controlled by YMTC, is tasked with stacking products from both lines. The post linked that structure to rules Beijing has applied since late December last year. Under those rules, newly approved factories must show in procurement tenders that at least half of their equipment is sourced domestically, with exemptions granted only when no domestic option is available. Schulz_Research said YMTC’s Wuhan Phase 3 is the first advanced memory project cleared under that framework and is set to begin production later this year. The note also outlined capacity figures for CXMT, YMTC and XMC, alongside market-share estimates and product updates including DDR5, LPDDR5 and planned HBM3 production.

Micron Technology plans to double its HBM production capacity to about 100,000 wafers per month by the end of 2026, up from 40,000-50,000 last year, aiming to narrow the gap with Samsung and SK Hynix. The company is ramping up HBM4 volume, which already exceeded $1 billion in cumulative revenue, and is investing in new facilities in Taiwan, Singapore, and Japan.

Google's senior director of supply chain infrastructure, Nikhil Cherian, revealed the company is developing both software and hardware solutions to address memory constraints in AI servers. The approach includes salvaging DDR4 modules from retired servers, designing custom adapters to connect older memory to next-generation servers, and importing retired servers for DDR4 removal. Cherian noted that AI has shifted from compute-constrained to memory-constrained, with high-performance memory consuming about 75% of an AI server's bill of materials. Goldman Sachs expects third-quarter PC DRAM prices to rise 18% to 23% and server DRAM 13% to 18%. Trendforce data shows spot prices for DDR4 8GB and DDR5 8GB reached $142 and $133 in August. Google's two new TPU ASICs this year feature memory-optimized designs, potentially reducing memory requirements by a factor of six, with the TPU8i chip packing 288GB of HBM3e memory.

TSMC expects to keep using conventional microbumps, not hybrid bonding, to link high-bandwidth memory with AI accelerators in advanced packaging over the near term, according to materials industry sources on Sept. 2. Finer-pitch microbumps are likely to remain in use through late HBM4 and into early HBM5, reflecting material development lead times. TSMC has asked materials and equipment partners to develop bonding and underfill solutions for roughly 5μm bumps, and Korean and Japanese suppliers have started work. Volume production for 5μm-class bumps is expected in the second half of 2028. Today's HBM3E bumps are about 15–25μm high, while HBM4 is approaching around 10μm. Japanese materials suppliers have said it is difficult to guarantee quality below 15μm. The push for shorter, finer bumps comes from height limits on HBM stacks and the need for denser interconnects. JEDEC caps HBM stack height at 775μm. In TSMC's CoWoS flow, GPU dies and preassembled HBM stacks attach to a silicon interposer via microbumps, while SK hynix and Samsung Electronics build the 16-layer DRAM die stacks in HBM packages. First- and second-generation HBM relied on larger solder bumps; microbumps became mainstream around the HBM3 generation. SK hynix uses MR-MUF, and Samsung Electronics uses TC-NCF. Hybrid bonding can make interconnects thinner and denser by directly bonding copper pads, and TSMC has applied it to logic stacking on its SoIC platform, but HBM still connects to the interposer through microbumps.

Crypto markets spent the past 24 hours balancing ETF flow data, shifting rate expectations and a fresh batch of regulatory and infrastructure developments. U.S. spot Bitcoin ETFs posted $201.9 million in net outflows on Aug. 28, ending a nine-session inflow streak that began in mid-August. Spot Ether ETFs moved the other way, taking in $102.1 million that day and stretching their run of positive flows to 10 straight sessions. According to SoSoValue, weekly flows still remained strong for both products, with Bitcoin funds adding $924 million over the Aug. 24-28 trading week and Ether funds bringing in $824 million. Macro pressure also remained in focus. Bitcoin held near $78,000 while the dollar strengthened and the yen slipped through 160 against the U.S. dollar. Ahead of Friday’s U.S. nonfarm payrolls report, CME FedWatch data showed traders assigning better-than-even odds to two Fed rate hikes this year. In parallel, Bank of England Governor Andrew Bailey warned G20 finance officials that frontier AI models could magnify cyber risks and expose already stretched financial markets to more severe disruptions. Elsewhere, Ireland moved to exclude crypto from a planned tax-advantaged investment account, Japan’s Financial Services Agency proposed easing reporting rules for trust-based stablecoins from fiscal 2027, and several market structure stories landed at once, from DTCC’s tokenization timeline and CME’s new crypto indexes to exchange inflows, venture financing, and fresh security incidents on Fogo and Cronos.

Chinese memory maker ChangXin Memory Technologies, or CXMT, has started small-batch production of HBM3E and plans to expand output in 2027, according to The Information, which cited two people familiar with the matter. The report said domestic chip teams including Cambricon and Alibaba’s T-Head have already been testing CXMT’s HBM products, and if those efforts go smoothly, the memory could appear in products as early as next year. HBM, or high-bandwidth memory, sits alongside AI chips and feeds them data at high speed, making it a critical component for AI computing. The report described HBM2 and later generations as a longstanding weakness for China’s domestic AI chip supply chain. In product-generation terms, CXMT is one step behind SK Hynix, Samsung and Micron, which are already mass-producing HBM4. Still, the report said small-batch production is not the same as mature mass production. CXMT’s HBM3E currently has lower yields, and its speed and reliability trail the three established suppliers. SK Hynix began mass production of HBM3E in 2024, and the three leading makers have already moved into HBM4 and started sampling HBM4E.